Anova Financial Networks seeks to accelerate the development of ultra-low latency transport devices! As a vertically integrated design and developer of ultra-low latency solutions, instruments, and systems, for High-Frequency Trading networks, our product portfolio includes, high resiliency fail-over and low-latency port-aggregation units.
The position is responsible for the design and development of advanced low-latency transport systems, from FPGA algorithm level up to full system integration. As part of a small team, engineers focus on new product development with the expectation to work with limited guidance on complex engineering activities in a fast-paced environment. The position conceives, designs, and prototypes FPGA-based hardware for IP data acquisition and post-processing of high-speed customer Ethernet traffic.
Activities include design documentation, prototype verification and debug, test development and transfer to customer network. This position requires troubleshooting of FPGA design, system problems and is committed to customer satisfaction. Although the location of the position is either in Chicago, IL, or Fremont, CA, from time to time it may be required to undertake duties at other Anova Financial Networks locations.
Essential Job Functions include the following, but are not limited to:
- Assist in the development of FPGA-based solutions for Ultra-low latency transport systems.
- FPGA programming in Verilog; Participates in cross-functional new product development teams as an FPGA design engineer.
- Assist in functional/performance testing for new FPGA designs.
- Assist in troubleshooting and determination of root cause FPGA algorithm failures.
- Participate in lab testing of prototype equipment and address FPGA performance improvements.
- Other FPGAs design activities may be added in the future as business conditions evolve.
- 3+ years of FPGA design experience required.
- Experience with FPGA-based data processing for high-speed real-time systems.
- Extensive experience with the FPGA firmware development process is a must; including Verilog code development, simulation, synthesis, and timing closure.
- Experience interfacing with high-speed peripherals such as external memory, SERDES transceivers, etc.
- Minimum of a B.S Degree in Electrical or Computer Engineering from an accredited university.
Specialized Knowledge and Skills:
- Strong sense of ownership and work ethic, written and verbal communication skills
- Strong ability to work well in a group atmosphere, and comply with high-quality standards
- Experience with Xilinx (Kintex) products and Vivado development tools.
- Experience with implementation and optimization of IP data processing algorithms in FPGA logic.